This invention relates to a power supply control system comprising a plurality of power supply units and is specifically directed to protect logic circuits connected to the power supply units from failure of over-voltage and under-voltage occurring in the power supply units. Such a power supply control system is particularly useful for a computer system.
Generally, the computer system comprises a power supply control system comprising a plurality of power supply units for generating a plurality of output voltages, such as -4.5 volts, -3 volts, and -2 volts, which are specified by lowest through highest voltages, respectively. The plurality of output voltages are supplied to a variety of units, such as processors, input/output units, and the like, which are implemented by logic circuits. In such a power supply control system, the plurality of power supply units are put into an on state in accordance with a power on sequence and put into an off state in accordance with a power off sequence. As will later be described, the power on sequence is for sequentially putting the plurality of power supply units into the on state in voltage increasing order of the output voltages of the plurality of power units. The power off sequence is for sequentially putting the plurality of power units into the off state in voltage decreasing order of the output voltages.
In the power supply control system, there is a case that one of the plurality of power supply units has failure, such as over-voltage or under-voltage. The power supply unit having the failure is called a failure power supply unit. In such a case, all of the plurality of power supply units should be put into the off state. Especially, it is desirable that the failure power supply unit is immediately put into the off state previous to other power supply units. In the conventional power supply control system, the plurality of power supply units are, however, put into the off state in accordance with the power off sequence described above even if the failure occurring in one of the plurality of power supply units. In this case, if the failure power supply unit is for generating the lowest output voltage, the failure power supply unit is put into the off state last in accordance with the power off sequence. This means that the logic circuits connected to the failure power supply unit are kept in an abnormal condition until the failure power supply unit is put into the off state. Under the condition, the logic circuits connected to the failure power supply unit often suffer damage from the failure power supply unit.